1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor filler is placed in a groove.
2. Description of the Related Art
FIG. 43 shows a cross sectional view of a transistor 102 of a previous art.
The transistor 102 is a trench-type power MOSFET and is provided with a semiconductor substrate 111 in which a silicon single crystal is doped with an N+-type impurity at a high concentration, and a drain layer 112 made of an N−-type silicon epitaxial layer formed on the semiconductor substrate 111 with an epitaxial growth technique.
The reference numeral 110 indicates a processed substrate having the semiconductor substrate 111 and the drain layer 112, and as a result of carrying out semiconductor manufacturing processes on the processed substrate 110, a p-type body layer 113 is formed on a surface side inside the drain layer 112, and pluralities of p+ type ohmic regions 116 and n+ type source regions 130 are formed at a surface vicinity inside the body layer 113.
The surface of the semiconductor substrate 110 is etched to a belt-shape at positions between the source regions 130, thus forming narrow grooves 120.
Gate insulating film 124 is formed on an inner side surface of the narrow grooves 120 and the narrow grooves 120 are filled with polysilicon in a non-contact state with the semiconductor substrate 110 due to the gate insulating film so that gate electrode plugs 127 are formed by the polysilicon.
The gate electrode plugs 127 inside the narrow grooves 120 are connected to each other by a gate electrode film made of a metal thin film not shown in the drawing.
A source electrode film 137 made of a metal thin film is formed on the surface of the source regions 130 and the ohmic regions 116. Interlayer insulating films 131 are formed on the narrow grooves 120, and the source electrode film 137 and the gate electrode plugs 127 are electrically insulated by the interlayer insulating films 131.
A drain electrode film 139 is formed on the back surface of the processed substrate 110; that is, on the surface of the semiconductor substrate 111.
The source electrode film 137 is connected to the ground potential; and when a positive voltage equal to or higher than a threshold voltage is applied to the gate electrode film while a positive voltage is applied to the drain electrode film 139, an n-type inversion layer is formed at the interface between the gate insulating film 124 and the body layer 113, and the source regions 130 and the drain layer 112 are connected by the inversion layer, with electric current flowing from the drain layer 112 to the source regions 130 via the inversion layer. This state is a state in which the transistor 102 is conductive, and since there is no JFET region, which are present in power MOSFET that do not use the narrow grooves 120, the conduction resistance is small compared to ordinary power MOSFET.
Further, when the electric potential of the gate electrode film changes from the conductive state to the same electric potential as the source electrode film 137, the inversion layer disappears so that electric current does not flow.
In this state, the pn junction between the body layer 113 and the drain layer 112 is under a reverse bias, and the avalanche breakdown voltage of the pn junction is equivalent to the withstanding voltage of the transistor 102.
Generally, the avalanche breakdown voltage of a pn junction varies depending on the state of the depletion layer under a reverse bias, but with the above-described transistor 102, since the electric field intensity within the depletion layer, which expands within the drain layer 112, is not uniform, the avalanche breakdown voltage is determined by the areas in which there is a strong electric field intensity so that the withstanding voltage is reduced.
Then, a semiconductor device 103 of a structure such as that shown in FIG. 44 has been proposed in which conductive-type embedded regions 122 different from the drain layer 112 are formed underneath the narrow grooves 120, which is an attempt to ease the electric field intensity of the depletion layer that expands in the drain layer 112.
The embedded regions 122 are formed by once cutting deeply the narrow grooves 120 and then growing a filler at the bottom portion and walls inside the narrow grooves 120, wherein a semiconductor single crystal and a semiconductor polycrystal are capable of being used as the filler.
Japanese Laid-Open Patent Publication No. 2003-69017 is a related art document of the present invention.
However, in this related art, when the embedded regions 122 are at a floating potential, the withstanding voltage is not stable. Obtaining the withstanding voltage by simulation, it was found out that the withstanding voltage is increased if the embedded regions 122 are short circuited to the source electrode film 137, and therefore a specific structure for that purpose has been required.
The present invention is devised to solve the above-described deficiencies of previous arts and it is an object thereof to provide a semiconductor device of high withstanding voltage.